6 .1 the encoder has an enable function for use in multiplexer applications. encoder and decoder forced idle facilities are provided forcing a 10101010..... pattern in encode and a v dd /2 bias in decode. the companding circuits may be operated with a 3 or 4-bit algorithm which is externally selected. the device may be put in the standby mode by selection of the powersave facility. a reference 1.024mhz oscillator uses an external clock or xtal. the FX619 is a low-power, 5 volt cmos device and is available in 22-pin cerdip dil, 24-lead/pin plastic and 28-lead ceramic leadless smt packages. FX619 'eurocom' delta codec cml semiconductor products product information the FX619 is an lsi circuit designed as a *continuously variable slope delta codec and is intended for use in military communications systems. designed to meet eurocom d1-ia8 with external components, the device is suitable for applications in military delta multiplexers, switches and phones. encoder input and decoder output filters are incorporated on-chip. sampling clock rates can be programmed to 16, 32 or 64 k bits/second from an internal clock generator or may be externally applied in the range 8 to 64 k bits/ second. sampling clock frequencies are output for the synchronization of external circuits. brief description fig.1 internal block diagram decoder data clock mode 2 mode 1 encoder data clock xtal data enable encoder force idle decoder input mod encoder input demod xtal/clock encoder output decoder output clock rate generators sampling rate control algorithm powersave 3 or 4-bit clock mode logic decoder force idle f 3 f 1 v ss v dd v bias f 0 f 1 f 2 FX619 publication d/619/6 september 1997 features/applications designed to meet eurocom d1-ia8 f meets stanag 4209 and stanag 4380 delta mux, switch and phone applications single chip full duplex codec military communications powersave facility single 5v cmos process full duplex cvsd* codec programmable sampling clocks 3 or 4-bit compand algorithm forced idle facility on-chip input and output filters
2 pin number function xtal/clock : input to the clock oscillator inverter. a 1.024mhz xtal input or externally derived clock is injected here. see clock mode pins and figure 3. no connection xtal : output of clock oscillator inverter. xtal circuitry shown is in accordance with cml application note d/xt/1 april 1986. no connection encoder data clock : a logic i/o port. external encode clock input or internal data clock output. clock frequency is dependant upon clock mode 1, 2 inputs and xtal frequency (see clock mode pins). encoder output : the encoder digital output, this is a three state output whose condition is set by data enable and powersave inputs as shown : data enable powersave encoder outpu t 1 1 enabled 0 1 high z (o/c) 1 0 vss no connection encoder force idle : when this pin is a logical '0' the encoder is forced to an idle state and the encoder digital output is 0101..., a perfect idle pattern. when this pin is a logical '1' the encoder encodes as normal. internal 1m w pullup. data enable : data is made available at the encoder output pin by control of this input. see encoder output pin. internal 1m w pullup. no connection bias : normally at v dd /2 bias, this pin requires to be externally decoupled by a capacitor, c 4 . internally pulled to v ss when "powersave" is a logical '0'. encoder input : the analogue signal input. internally biased at v dd /2, external components are required on this input. the source impedance should be less than 100 w , output idle channel noise levels will improve with an even lower source impedance. see fig. 3. v ss : negative supply. FX619 j 1 2 3 4 5 6 7 8 9 10 11 FX619 l1/l2 1 2 3 4 5 6 7 8 9 10 11 12 FX619 m1 1 2 3 4 5 6 7, 8 9 10 11 12 13 14
3 pin number function no connection decoder output : the recovered analogue signal is output at this pin, it is the buffered output of a bandpass filter and requires external components. during "powersave" this output is o/c. no connection powersave : a logical '0' at this pin puts most parts of the codec into a quiescent non- operational state. when at a logical '1' the codec operates normally. internal 1m w pullup. no connection decoder force idle : a logical '0' at this pin gates a 0101...pattern internally to the decoder so that the decoder output goes to v dd /2. when this pin is at a logical '1' the decoder operates as normal. internal 1m w pullup. decoder input : the received digital signal input. internal 1m w pullup. decoder data clock : a logic i/o port. external decode clock input or internal data clock output, dependant upon clock mode 1, 2 inputs, see clock mode pins. algorithm : a logical '1' at this pin sets this device for a 3-bit companding algorithm. a logical '0' sets a 4-bit companding algorithm. internal 1m w pullup. clock mode 2 : clock mode 1 clock mode 2 facility clock mode 1 : 0 0 external clocks internal 1m w 0 1 internal, 64kb/s = f ? 16 pullups. 1 0 internal, 32kb/s = f ? 32 1 1 internal, 16kb/s = f ? 64 clock rates refer to f = 1.024 mhz xtal/clock input. during internal operation the data clock frequencies are available at the ports for external circuit synchronization. independant or common data rate inputs to encode and decode data clock ports may be employed in the external clocks mode. v dd : positive supply. a single + 5 volt power supply is required. FX619 l1/l2 13 14 15 16 17 18 19 20 21 22 23 24 FX619 j 12 13 14 15 16 17 18 19 20 21 22 FX619 m1 15,16 17 18,19 20 21 22 23 24 25 26 27 28
4 codec integration fig.3 recommended external components fig.2 eurocom system configuration C showing the FX619, which with the indicated interfacing, will conform to the eurocom basic parameters specification d1 C ia8. eurocom analogue input interface (balun & buffer) eurocom input eurocom output regulated power supply synchronous clock and data system FX619 parameters measured here FX619 parameters measured here 1.024 mhz 1.024 mhz data clock mode 16/32/64kb/s eurocom analogue output interface (balun & buffer) FX619 encoder FX619 decoder data clocks clocks component unit value note C with reference to figure 3 (below) r 1 1m oscillator inverter bias resistor. r 2 selectable xtal drive limiting resistor. c 1 33p xtal circuit drain capacitor. c 2 33p xtal circuit gate capacitor. c 3 1.0 m encoder input coupling capacitor C the drive source impedance to this input should be less than 100 w . output idle channel noise levels will improve with an even lower source impedance. c 4 1.0 m bias decoupling capacitor. c 5 1.0 m v dd decoupling capacitor. x 1 1.024 mhz a 1.024 mhz xtal/clock input will yield exactly 16/32/64 kb/s data clock rates. xtal circuitry shown is in accordance with cml application note d/xt/1 april 1986. tolerance :C resistors 10% capacitors 20% FX619j 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 r 1 r 2 c 2 c 1 x 1 xtal/clock xtal n/c encoder data clock encoder output data enable n/c bias encoder input v ss v dd c 3 c 4 clock mode 1 clock mode 2 algorithm decoder data clock decoder input decoder force idle powersave n/c decoder output n/c c 5 v dd encoder force idle ss v
5 typical test sample rate bit sequence at decoder input mla output duty cycle level a. 16kbit/s 10110100100100101101 0 - 41.5dbm0 32kbit/s 1011011010101001001001001001010101101101 0 - 42.0dbm0 b. 16kbit/s 11011001001001001101 0.05 - 25.0dbm0 32kbits 1011011010101001001000100100101011011011 0.05 - 25.0dbm0 c. 16kbits 10110101000100101011 0.1 - 19.0dbm0 32kbit/s 1101101101010010001000100100101011011101 0.1 - 18.5dbm0 d. 16kbit/s 11011001000010011011 0.2 - 11.0dbm0 32kbit/s 1101110110010100010000100010011010111011 0.2 - 11.5dbm0 e. 16kbit/s 11011010000010010111 0.3 - 6.5dbm0 32kbit/s 1110111011001000100000010001001101110111 0.3 - 6.5dbm0 f. 16kbit/s 11011010000001001111 0.4 - 3.0dbm0 32kbit/s 1111011101010001000000001000101011101111 0.4 - 3.0dbm0 g. 16kbit/s 11101010000000101111 0.5 0dbm0 32kbit/s 1111101110100010000000000100010111011111 0.5 0dbm0 table 1 bit sequence test table codec performance ...... using the bit sequence tests (a to g) at the decoder input pin in accordance with the eurocom specification d1 C ia8, the decoder output is as shown in table 1. codec timing information decoder timing encoder timing multiplexing function high z high z t dr t df data true time t su t h data clocked t cl data clocked t ch t if t ir t pco t ch encoder clock encoder data output decoder clock decoder data input encoder output data enable fig.4 codec timing diagrams timing t ch clock '1' pulse width 1.0 m s min. t cl clock '0' pulse width 1.0 m s min. t ir clock rise time 100ns typ. t if clock fall time 100ns typ. t su data set-up time 450ns min. t h data hold time 600ns min. t su + t h data true time. t pco clock to output delay time 750ns max. t dr data rise time 100ns typ. t df data fall time 100ns typ. xtal input frequency 1.024mhz.
6 fig.5 gain vs input level (16kbit/s) fig.6 gain vs input level (32kbit/s) fig.8 s/n vs input level (32kbit/s) fig.7 s/n vs input level (16kbit/s) fig.9 attenuation distortion vs frequency (16kbit/s) codec performance ...... relative to the eurocom specification d1 - ia8 input level (dbm0) - 40 - 30 - 20 - 10 0 8 10 15 20 s/n ratio (db) ref: 0dbm0 input level = 489mvrms input frequency = 820hz attenuation (db) 0 1 - 1 2 3 - 2 - 3 10 0 - 10 - 20 - 30 - 40 - 50 input level (dbm0) ref: 0dbm0 input level = 489mvrms input frequency = 820hz ref. attenuation (db) 0 1 - 1 2 3 - 2 - 3 10 0 - 10 - 20 - 30 - 40 - 50 input level (dbm0) ref. ref: 0dbm0 input level = 489mvrms input frequency = 820hz input level (dbm0) - 40 - 30 - 20 - 10 0 25 15 20 s/n ratio (db) ref: 0dbm0 input level = 489mvrms input frequency = 820hz frequency (khz) - 50 - 40 - 30 - 20 - 10 0 + 10 gain (db) - 60 0123456 0.3 2.6 1.5 1.5 input level = -20dbm0
7 codec performance ...... relative to the eurocom specification d1 - ia8 fig.14 attenuation distortion vs frequency (32kbit/s) fig.10 s/n vs input frequency (16kbit/s) fig.12 principal integrator response fig.13 compand envelope fig.11 s/n v s input frequency (32kbit/s) frequency (khz) - 50 - 40 - 30 - 20 - 10 0 + 10 gain (db) - 60 0123456 0.3 1.4 2.6 3.4 2 3 input level = -20dbm0 input frequency (khz) 0 1 2 3 5 10 15 20 s/n ratio (db) 25 30 input level = -20dbm0 frequency (hz) amplitude (db) 0 - 6 - 12 - 18 - 24 - 30 10 100 1k 10k - 6db/octave time (ms) amplitude 1.0 8.76 5.76 0.00794 0.1 0.397 0.9 amplitude of test signal (g) - table 1. beginning of discharge amplitude of test signal (a) input frequency (khz) 0 1 2 3 5 10 15 20 s/n ratio (db) input level = -20dbm0
8 specifications absolute maximum ratings exceeding the maximum rating can result in device damage. operation of the device outside the operating limits is not implied. supply voltage -0.3 to 7.0v input voltage at any pin (ref v ss = 0v) -0.3 to (v dd + 0.3v) source/sink current (supply pins) 30ma (other pins) 20ma total device dissipation @ 25 c 800mw max. derating (j and m1 packages) 10mw/ c derating (l1 and l2 packages) 13mw/ c operating temperature range: FX619j -40 c to +85 c (cerdip) FX619l1/l2 -40 c to +85 c (plastic) FX619m1 -40 c to +85 c (cerquad) storage temperature range: FX619j -55 c to +125 c (cerdip) FX619l1/l2 -40 c to +85 c (plastic) FX619m1 -55 c to +125 c (cerquad) operating limits all characteristics are measured using the following parameters unless otherwise specified: v dd = 5.0v, t amb = 25 c, xtal/clock f 0 = 1.024mhz, audio level 0db ref (0dbm0) = 489 mv rms. audio test frequency = 820 hz. sample clock rate = 32kb/s. compand algorithm = 3-bit. characteristics see note min. typ. max. unit static values supply voltage 1 4.5 5.0 5.5 v supply current (enabled) C 4.5 C ma supply current (powersave) C 1.0 C ma inputs logic '1' 8 3.5 C C v inputs logic '0' 8 C C 1.5 v outputs logic '1' 8 4.0 C C v outputs logic '0' 8 C C 1.0 v digital input impedance (logic i/o pins) 1.0 10 C m w digital input impedance (logic input pins, pullup resistor) 2 300 C C k w digital output impedance C C 4 k w analogue input impedance 4 1 C k w analogue output impedance 7 C C 800 w three state output leakage current (output disabled) -4 C +4 m a insertion loss 3 -2 C +2 db dynamic values 1 encoder: analogue signal input levels 5,9 -35 C +6 dbm0 principle integrator frequency C 275 C hz encoder passband 3400 hz compand time constant C 4 C ms decoder: analogue signal output levels 5,9 -35 C +6 dbm0 decoder passband 300 C 3400 hz encoder decoder (full codec): compression ratio (cd = 0.5 to cd = 0.0) C 50 C passband 300 C 3400 hz stopband 6 C 10 khz stopband attenuation C 60 C db passband gain C 0 C db passband ripple (300hz C1400hz) -1 C +1 db (1400hz C 2600hz) -1 C +3 db (2600hz C 3400hz) -2 C +3 db output noise (input short circuit) 9 C C -62 dbm0p perfect idle channel noise (encoder forced) 9 C -63 C dbm0p group delay distortion 6 (1000hz to 2600hz) C C 450 m s (600hz to 2800hz) C C 750 m s (500hz to 3000hz) C C 1.5 ms xtal/clock frequency 500 1024 1500 khz C notes to be used with these specifications are detailed on page 9 (overleaf) ? ? ? ?
9 specifications ...... notes: 1. dynamic characteristics are specified at 5v unless otherwise specified. 2. all logic inputs except, encoder and decoder data clocks. 3. for an encoder/decoder combination, insertion loss contributed by a single component is half this figure. 4. driven with a source impedance of <100 w . 5. recommended values C see figures 5, 6, 7 and 8. 6 group delay distortion for the full codec is relative to the delay with 820hz, -20db at the encoder input. 7. an emitter follower output stage. 8. 4v = 80% v dd , 3.5v = 70% v dd , 1.5v = 30% v dd , 1v = 20% v dd . 9. analogue voltage levels used in this data sheet: 0dbm0 = 489mvrms = - 4dbm = 0db. - 20dbm0 = 49mvrms = - 24dbm. (e) inputs and outputs should be screened wherever possible. (f) a "ground plane" connected to v ss will assist in eliminating external pick-up on the input and output pins. (g) it is recommended that the power supply rails have less than 1mvrms of noise allowed. (h) the source impedance to the encoder input pin must be less than 100 w , output idle channel noise levels will improve with even lower source impedances. (a) care should be taken on the design and layout of the printed circuit board. (b) all external components (as recommended in figure 3) should be kept close to the package. (c) tracks should be kept short, particularly the encoder input capacitor and the v bias capacitor. (d) xtal/clock tracks should be kept well away from analogue inputs and outputs. application recommendations due to the very low levels of signal and idle channel noise specified in the eurocom basic parameters specification d1 C ia8 C a noisy or badly regulated power supply could cause instability putting the overall system performance out of specification. adherence to the points noted below will assist in minimizing this problem. process information the following table gives details of the process and test controls employed in the manufacture of the FX619 eurocom delta codec in j and m1 packages only. l1 and l2 products are supplied without the process and test controls detailed below. function reference remarks hermeticity fine leak test C mil std 883c using method 1014 C test condition a1. coarse leak test C mil std 883c using method 1014 C test condition c. burnin mil std 883c using method 1015 C test condition e. 168 hours @ 85 c with 5v power, and clocks applied. temperature cycling mil std 883c using method 1010 C test condition b. 10 cycles -55 c to +125 c. the following mechanical assembly tests are qualified to bs9450 vibration bs9450 section 1.2.6.8.1 55hz to 500hz at 98 m/sec acceleration. shock bs9450 section 1.2.6.6 981 m/sec for 6 msec. low pressure bs9450 section 1.2.6.12 transport and storage C 225mmhg (altitude 9000m). operation C 600mmhg (altitude 2400m). humidity bs9450 section 1.2.6.4 96 hours @ 45 c, 95% relative humidity plus condensed water.
package outlines the FX619 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. handling precautions the FX619 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. 10 ordering information FX619j 22-pin cerdip dil (j3) FX619l1 24-pin quad plastic encapsulated bent and cropped (lg) not to scale max. body length 27.38mm max. body width 9.75mm FX619j 22-pin cerdip dil (j3) not to scale max. body length 10.25mm max. body width 10.25mm FX619l1 24-pin quad plastic encapsulated bent and cropped (lg) not to scale max. body length 10.40mm max. body width 10.40mm FX619l2 24-pin plastic leaded chip carrier (ls) not to scale max. body length 11.60mm max. body width 11.60mm FX619m1 28-lead ceramic leaded chip carrier (m1) FX619l2 24-pin plastic leaded chip carrier (ls) FX619m1 28-lead ceramic leaded chip carrier (m1)
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